The disclosure relates generally to structures and manufacturing processes for junctionless tunnel field effect transistors (FETs). More specifically, embodiments of the present disclosure include a junctionless tunnel FET structure with a metal-insulator transition material therein, and processes for fabricating the junctionless tunnel FET structure.
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. A conventional transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the ability for electric current to flow between the source and the drain can be turned on and off. A common type of transistor is a field effect transistor (FET). A FET can include a gate structure, typically composed of polysilicon and/or a metal, formed on and contacting an insulator placed on top of the semiconductor layer positioned between the source and the drain. The semiconductor layer can include various dopants therein, with one type of doping adjacent to the source, and another type of doping (i.e., complementary doping) adjacent to the drain, to form a p-n junction. By applying a voltage to the gate structure, an electrically conductive channel can be created within the semiconductor layer between the source and drain terminals.
For particular implementations, the design of a FET can be adapted to provide different characteristics. One alternative type of FET structure, known as a junctionless FET, includes a semiconductor layer, with a single type (i.e., p+ or n−) of doping, positioned between a source and drain. Although a junctionless FET is relatively simple to fabricate, the sub-threshold slope (i.e., the change in gate voltage required to increase the source to drain current by one order) may be limited due to conventional over the barrier carrier transport. Another alternative FET structure, known as a tunnel FET, can include a gate contact separated from a buried semiconductor layer by an interconnect material (e.g., doped polycrystalline silicon). The buried semiconductor layer can include multiple types of semiconducting materials and dopants, such that controlling a voltage of the gate influences current flow between a source contact and a drain contact at two ends of the buried semiconductor layer. A tunnel FET may have limited opportunities for use because fabricating the various semiconductor materials and introducing dopants to the buried semiconductor layer can increase manufacturing costs and complexity.